View UT8CR512K32-17VWX_1333065.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Standard Products
UT8CR512K32 16 Megabit SRAM
Advanced Data Sheet October 2004 www.aeroflex.com/4MSRAM
FEATURES 17ns maximum access time Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs CMOS compatible inputs and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volts, 1.8 volt core Radiation performance - Intrinsic total-dose: 300 Krad(Si) - SEL Immune >100 MeV-cm2/mg - LETth (0.25): 53.0 MeV-cm2/mg - Memory Cell Saturated Cross Section 1.67E-7cm2/bit - Neutron Fluence: 3.0E14n/cm2 - Dose Rate - Upset 1.0E9 rad(Si)/sec - Latchup 1.0E11 rad(Si)/sec Packaging options: - 68-lead ceramic quad flatpack (20.238 grams with lead frame) Standard Microcircuit Drawing 5962-04227 - QML compliant part
INTRODUCTION The UT8CR512K32 is a high-performance CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 words by 8 bit SRAMs with common output enable. Easy memory expansion is provided by active LOW chip enables (EN), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. Writing to each memory is accomplished by taking the corresponding chip enable (En) input LOW and write enable (Wn) input LOW. Data on the I/O pins is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking the chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The input/output pins are placed in a high impedance state when the device is deselected (En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by making Wn along with En a common input to any combination of the discrete memory die. W2 E1 W1 W0 E0
E3 A(18:0) G
W3
E2
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24) or DQ3(7:0)
DQ(23:16) or DQ2(7:0)
DQ(15:8) or DQ1(7:0)
DQ(7:0) or DQ0(7:0)
Figure 1. UT8CR512K32 SRAM Block Diagram
1
VDD1 A0 A1 A2 A3 A4 A5 E2 VSS E3 W0 A6 A7 A8 A9 A10 VDD2
DEVICE OPERATION
DQ0(2) DQ1(2) DQ2(2) DQ3(2) DQ4(2) DQ5(2) DQ6(2) DQ7(2) VSS DQ0(3) DQ1(3) DQ2(3) DQ3(3) DQ4(3) DQ5(3) DQ6(3) DQ7(3)
DQ0(0) DQ1(0) DQ2(0) DQ3(0) DQ4(0) DQ5(0) DQ6(0) DQ7(0) VSS DQ0(1) DQ1(1) DQ2(1) DQ3(1) DQ4(1) DQ5(1) DQ6(1) DQ7(1)
68 67 66 65 64 63 62 61 60 59 58 57 56 555453 52 1 51 2 50 3 49 4 48 5 47 Top View 6 46 7 45 8 44 9 43 10 42 11 41 12 40 13 39 14 38 15 37 16 36 17 35 1819 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VDD2 A11 A12 A13 A14 A15 A16 E0 G E1 A17 W1 W2 W3 A18 VDD1 VSS
Each die in the UT8CR512K32 has three control inputs called Enable (En), Write Enable (Wn), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The device enable (En) controls device selection, active, and standby modes. Asserting En enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to each memory die by selecting the 2,048,000 byte of memory. Wn controls read and write operations. During a read cycle, G must be asserted to enable the outputs. Table 1. Device Operation Truth Table G X X 1 0 WN X 0 1 1 EN 1 0 0 0 I/O Mode 3-state Data in 3-state Data out Mode Standby Write Read2 Read
Figure 2. 17ns SRAM Pinout 68) PIN NAMES A(18:0) DQ(7:0) EN W G VDD1 VDD2 VSS Address Data Input/Output Enable Write Enable Output Enable Power (1.8V) Power (3.3V) Ground
Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than VIH (min) with En and G less than VIL (max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. SRAM read Cycle 1, the Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and Wn deasserted. Valid data appears on data outputs DQn(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). SRAM read Cycle 2, the Chip Enable-controlled Access is initiated by En going active while G remains asserted, Wn remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQn(7:0). SRAM read Cycle 3, the Output Enable-controlled Access is initiated by G going active while En is asserted, Wn is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.
2
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than VIH(min), or when Wn is less than VIL(max). Write Cycle 1, the Write Enable-controlled Access is defined by a write terminated by Wn going high, with En still active. The write pulse width is defined by tWLWH when the write is initiated by Wn, and by tETWH when the write is initiated by En. Unless the outputs have been previously placed in the highimpedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQn(7:0) to avoid bus contention. Write Cycle 2, the Chip Enable-controlled Access is defined by a write terminated by the former of En or Wn going inactive. The write pulse width is defined by tWLEF when the write is initiated by Wn, and by tETEF when the write is initiated by the En going active. For the Wn initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQn (7:0) to avoid bus contention.
RADIATION HARDNESS
The UT8CR512K32 SRAM incorporates special design and layout features which allows operation in a limited radiation environment. Table 2. Radiation Hardness Design Specifications1 Total Dose Heavy Ion Error Rate2 300K 8.9x10-10 rad(Si) Errors/Bit-Day
Notes: 1. The SRAM is immune to latchup to particles >100MeV-cm2/mg. 2. 10% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum.
Supply Sequencing
No supply voltage sequencing is required between VDD1 and VDD2.
3
ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL VDD1 VDD2 VI/O TSTG PD TJ JC II PARAMETER DC supply voltage DC supply voltage Voltage on any pin Storage temperature Maximum power dissipation Maximum junction temperature2 Thermal resistance, junction-to-case3 DC input current LIMITS -0.3 to 2.0V -0.3 to 3.8V -0.3 to 3.8V -65 to +150C 1.2W +150C 5C/W
5 mA
Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS SYMBOL VDD1 VDD2 TC VIN PARAMETER Positive supply voltage Positive supply voltage Case temperature range DC input voltage LIMITS 1.7 to 1.9V 3.0 to 3.6V (C) Screening: -55 to +125C (W) Screening: -40 to +125C 0V to VDD2
4
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)* (-55C to +125C for (C) screening and -40C to 125C for (W) screening) SYMBOL VIH VIL VOL1 VOH1 CIN1 CIO1 IIN IOZ PARAMETER High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input capacitance Bidirectional I/O capacitance Input leakage current Three-state output leakage current Short-circuit output current IOL = 8mA,VDD2 =VDD2 (min) IOH = -4mA,VDD2 =VDD2 (min) = 1MHz @ 0V = 1MHz @ 0V VIN = VDD2 and VSS VO = VDD2 and VSS, VDD2 = VDD2 (max) G = VDD2 (max) VDD2 = VDD2 (max), VO = VDD2 VDD2 = VDD2 (max), VO = VSS Inputs : VIL = VSS + 0.2V VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) Inputs : VIL = VSS + 0.2V, VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) Inputs : VIL = VSS + 0.2V VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) Inputs : VIL = VSS + 0.2V, VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) CMOS inputs , IOUT = 0 EN = VDD2 -0.2 VDD1 = VDD1 (max), VDD2 = VDD2 (max) CMOS inputs , IOUT = 0 EN = VDD2 - 0.2 VDD1 = VDD1 (max), VDD2 = VDD2 (max) -2 -2 .8*VDD2 12 12 2 2 CONDITION MIN .7*VDD2 .3*VDD2 .2*VDD2 MAX UNIT V V V V pF pF A A
IOS2, 3
-100
+100
mA
IDD1(OP1)
Supply current operating @ 1MHz
45
mA
IDD1(OP2)
Supply current operating @66MHz
93
mA
IDD2(OP1)
Supply current operating @ 1MHz
243
A
IDD2(OP2)
Supply current operating @66MHz
12
mA
IDD1(SB)4 IDD2(SB)4 IDD1(SB)4 IDD2(SB)4
Supply current standby @ 0Hz
38 100 38 100
m A m A
Supply current standby A(18:0) @ 66MHz
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si). 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. VIH = VDD2 (max), VIL = 0V.
5
AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)* (-55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = VDD1 (min), VDD2 = VDD2 (min)) SYMBOL PARAMETER
8CR512-155 MIN MAX
UNIT
tAVAV1 tAVQV tAXQX2 tGLQX1,2 tGLQV tGHQZ2 tETQX2,3 tETQV3 tEFQZ4
Read cycle time Read access time Output hold time G-controlled output enable time G-controlled output enable time G-controlled output three-state time E-controlled output enable time E-controlled access time E-controlled output three-state time2
17 17 3 0 7 7 5 17 7
ns ns ns ns ns ns ns ns ns
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Guaranteed, but not tested. 2. Three-state is defined as a 200mV change from steady-state output voltage. 3. The ET (enable true) notation refers to the latter falling edge of EN. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the latter rising edge of EN. SEU immunity does not affect the read parameters.
6
tAVAV A(18:0)
DQn(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: 1. En and G < VIL (max) and Wn > VIH (min)
tAXQX Figure 3a. SRAM Read Cycle 1: Address Access
A(18:0) En tETQV DQn(7:0) tETQX tEFQZ
DATA VALID
Assumptions: 1. G < VIL (max) and Wn > VIH (min)
Figure 3b. SRAM Read Cycle 2: Chip Enable-Controlled Access
tAVQV A(18:0) G tGHQZ tGLQX DQn(7:0)
Assumptions: 1. En < VIL (max) and Wn > VIH (min)
DATA VALID
tGLQV
Figure 3c. SRAM Read Cycle 3: Output Enable-Controlled Access
7
AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)* (-55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = VDD1 (min), VDD2 = VDD2 (min)) SYMBOL PARAMETER
8CR512-15 MIN MAX
UNIT
tAVAV1 tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ2 tWHQX2 tETEF tDVWH tWHDX tWLEF tDVEF tEFDX tAVWH tWHWL1
Write cycle time Device enable to end of write Address setup time for write (EN- controlled) Address setup time for write (W - controlled) Write pulse width Address hold time for write (W - controlled) Address hold time for device enable (EN- controlled) W - controlled three-state time W - controlled output enable time Device enable pulse width (EN - controlled) Data setup time Data hold time Device enable controlled write pulse width Data setup time Data hold time Address valid to end of write Write disable time
17 12 0 0 12 2 0 5 4 12 7 2 12 7 0 12 3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Test with G high. 2. Three-state is defined as 200mV change from steady-state output voltage.
8
A(18:0)
En tAVWH tETWH Wn tAVWL Qn(7:0) tWLQZ Dn(7:0)
Assumptions: 1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be in three-state for the entire cycle. APPLIED DATA
tWHWL tWHAX
tWLWH
tWHQX
tDVWH
tWHDX
Figure 4a. SRAM Write Cycle 1: Write Enable - Controlled Access
9
A(18:0) tAVET tETEF tEFAX En
or
tAVET En tWLEF
APPLIED DATA
tETEF tEFAX
Wn Dn(7:0)
tWLQZ Qn(7:0)
tDVEF
tEFDX
Assumptions & Notes: 1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle. 2. Either En scenario above can occur.
Figure 4b. SRAM Write Cycle 2: Chip Enable - Controlled Access
10
DATA RETENTION CHARACTERISTICS (Pre-Radiation)3 (VDD2 = VDD2 (min), 1 Sec DR Pulse) SYMBOL VDR IDDR 1 Device Type 1 IDDR 1 Device Type 2 tEFR1,2 tR1,2 Data retention current PARAMETER VDD1 for data retention Data retention current 1.0 -55C 25C 125C -40C 25 125C 0 tAVAV MINIMUM 1.0 -MAXIMUM -600 600 30 600 600 30 UNIT V A A mA A A mA ns ns
--
Chip deselect to data retention time Operation recovery time
0 tAVAV
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. EN = VDD2 all other inputs = VDD2 or VSS 2. VDD2 = 0 volts to VDD2 (max)
DATA RETENTION MODE 1.7V VDD1 tEFR VSS EN
VIN <0.3VDD2 CMOS
1.7V VDR > 1.0V
tR
VIN >0.7VDD2 CMOS
VDD2
Figure 5. Low VDD Data Retention Waveform
CMOS VDD2-0.05V 188 ohms 1.4V 0.0V 10% 90%
< 2ns 50pF Input Pulses
< 2ns
Notes: 1. 50pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD2/2).
Figure 6. AC Test Loads and Input Waveforms
11
PACKAGING
Notes: 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF38535. 4. Ceramic shall be dark alumina. 5. Letter designations are to cross reference to MIL-STD-1835. 6. Dogleg geometries are optional within dimensions shown. 7. These areas may have notches and tabs different than shown. 8. Lead true position tolerances and coplanarity are not measured. 9. Packages may be shipped with repaired leads as shown. Coplanarity requirements do not apply in the repaired area. 10. Numbering and lettering on the ceramic are not subject to visual or marking criteria.
Figure 7. 68-pin Ceramic FLATPACK
12
ORDERING INFORMATION 512K32 SRAM:
UT **** * - * *
***
Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (-55C to +125C) (P) = Prototype flow (W) = Extended industrial temperature range flow (-40C to +125C) Package Type: (V) = 68-lead ceramic FP Access Time: (17) = 17ns access time
Device Type: (8CR512K32) = 512K x 32SRAM
Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither tested nor guaranteed.
13
512K x 32 SRAM: SMD
5962 - 04227 ***
* * ** *
Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (V) = 68-lead ceramic flatpack
Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type (01) = 17ns access time, CMOS I/O, 68-lead flatpack package (-55C to +125C) (02) = 17ns access time, CMOS I/O, 68-lead flatpack package (-40C to +125C) (02TBD)=15ns access time, CMOS I/O, 40-lead flatpack package, dual chip enable (not available) Drawing Number: 04227 Total Dose: (R) = 100K rad(Si) (F) = 300K rad(Si)
Federal Stock Class Designator: No options
Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
14
NOTES
15
COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254
INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266
NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468
www.aeroflex.com
info-ams@aeroflex.com
Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.
Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused
16

▲Up To Search▲

Price & Availability of UT8CR512K32-17VWX

	To Download UT8CR512K32-17VWX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .